1. Field of the Invention
The present invention relates in general to wafer-level integrated circuit (IC) testers, and in particular to a method for verifying signal paths through a structure interconnecting an IC tester to an IC wafer to be tested.
2. Description of Related Art
Many integrated circuit (IC) testers test ICs while the ICs are still in the form of die on a semiconductor wafer. A typical wafer tester includes a chassis called a “test head” containing printed circuit boards implementing the circuits that test a wafer. The test circuits are usually organized into a set of similar “channels”, with each channel including all the circuitry needed to generate a test signal input to one test point on the wafer and to monitor any wafer output signal produced at that test point. Each channel usually has a single bi-directional input/output (I/O) port though which it communicates with the wafer test point, though some employ two unidirectional ports.
An interconnect structure residing between the test head and the wafer provides signal paths between the channels' I/O ports and test points on the wafer. Interconnect structures make contact with the test head I/O ports and the wafer test points in various ways. For example with the test head residing above the interconnect structure, a channel's I/O port may access contact pads on an upper surface of a interconnect structure via a set of pogo pin connectors extending downward from the test head. The interconnect structure in turn may access the test points of the IC die via a set of small probes. The probes may be attached to an under surface of an interconnect structure and may contact pads on the upper surface of the wafer when the wafer is moved into position under the interconnect structure. Alternatively, the probes may be implemented as spring contacts formed on the surface of the wafer itself, with tips of the spring contacts accessing contact pads on the under surface of interconnect structure.
Since the test head is relatively large, the tester channels' I/O ports are distributed over a much wider horizontal area than the test points on the relatively small IC die they must access. Thus regardless of how the interconnect structure is implemented, it must provide a large number of signal paths extending in both horizontal and vertical directions in order to interconnect the channel I/O ports to the test points on the wafer. Thus the interconnect structure is often a relatively complicated structure including more than one interconnected signal routing layer. The signal paths through the interconnect structure may also include components such as small resistors or capacitors.
Before testing a wafer we would like to confirm that the interconnect structure can provide the necessary signal paths between the test head and the wafer. A connection failure may arise, for example, due to a misalignment of pogo pins or probes with their intended contact points, a broken, missing or contaminated pogo pin, probe or contact pad, a misalignment between contact structures within internal layers within the interconnect structure, an open circuit or short circuit fault between conductors within the interconnect structure or within the test head, or defective or missing discrete components in the signal paths through the interconnect structure. In many applications we also would like to verify that the resistance of a signal path between each test head I/O port and a corresponding test point on wafer is within acceptable limits. Contactor assemblies are usually designed to provide signal paths having particular resistances, and any variation from the intended resistance, due for example to corrosion or contamination on contact pads or the tips of probes or pogo pins, can distort test results.
Shorts, continuity and resistances of signal paths within a interconnect structure are usually tested during the manufacturing process using conventional resistance and continuity testing equipment accessing opposite ends of the signal paths via small probes. However signal paths within a probe assembly can later fail when in use in an integrated circuit tester, and it is difficult and inconvenient to periodically remove a probe assembly from a tester and manually test the continuity and resistance of its signal paths. Open and short circuit signal path failures can often be detected, or at least suspected, because they usually lead to characteristic patterns of IC test failures. However when a signal path has a resistance that is marginally out of an acceptable range, wafer test failures may not exhibit a clear pattern, and die can be improperly rejected as failing a test when the source of the failure was in fact the interconnect structure.
What is needed is a convenient method for quickly testing for shorts, continuity and resistances of signal paths through a interconnect structure without having to remove it from its working environment.